Field
This disclosure generally relates to superconducting integrated circuits and particularly relates to testing and packaging superconducting integrated circuit chips.
Superconducting Processor
A superconducting integrated circuit may take the form of a superconducting processor, where the superconducting processor may be a classical processor or a quantum processor. A superconducting quantum processor may make use of quantum effects such as quantum tunneling, superposition, and/or entanglement whereas a superconducting classical processor may not make use of these effects, but may rather operate by emphasizing different principles, such as for example the principles that govern the operation of semiconducting classical processors. However, there may still be certain advantages to the implementation of such superconducting “classical” processors. Due to their natural physical properties, superconducting classical processors may be capable of higher switching speeds and shorter computation times than non-superconducting processors, and therefore it may be more practical to solve certain problems on superconducting classical processors. The present systems and methods are particularly well-suited for use with both superconducting quantum processors and superconducting classical processors.
Quantum Processor
A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of physical qubits and associated local bias devices, for instance two or more superconducting qubits. A superconducting quantum processor may also employ coupling devices (i.e., “couplers”) providing communicative coupling between qubits. Further details and embodiments of exemplary quantum processors that may be used in conjunction with the present systems and devices are described in, for example but not limited to, U.S. Pat. No. 7,533,068, U.S. Pat. No. 8,008,942, U.S. Pat. No. 8,195,596, U.S. Pat. No. 8,190,548, and US Patent Publication 2011-0022820.
Integrated Circuit Fabrication and Packaging
Traditionally, the fabrication and packaging of superconducting integrated circuits has not been performed at state-of-the-art semiconductor fabrication facilities. This may be due to the fact that some of the materials used in superconducting integrated circuits can contaminate the semiconductor facilities. For instance, gold may be used as a resistor in superconducting circuits, but gold can contaminate a fabrication tool used to produce CMOS wafers in a semiconductor facility. Consequently, superconducting integrated circuits containing gold are typically not processed by tools which also process CMOS wafers.
Superconductor fabrication and packaging has typically been performed in research environments where standard industry practices could be tailored for superconducting circuit production. Due to issues associated with superconducting circuits, not all semiconductor processes and techniques are necessarily transferrable to superconductor chip production. Transforming semiconductor processes and techniques for use in superconductor chip and circuit fabrication often requires changes and fine adjustments. Such changes and adjustments typically are not obvious and may require a great deal of experimentation. The semiconductor industry faces problems and issues not necessarily related to the superconducting industry. Likewise, problems and issues that concern the superconducting industry are often of little or no concern in standard semiconductor fabrication.
Solder Bump Bonding
A solder bump is a small sphere/hemisphere of solder that is used for establishing a “bond” (i.e., an electrical connection) between two electrical current paths (e.g., between an electrical device and a bonding pad/contact area). Solder bump bonding is a widely used technique in the semiconductor industry but is considerably less developed in the superconductor industry. Two important challenges in the superconductor industry are: establishing continuous, uninterrupted superconductive electrical connections through solder bumps and providing solder bumps of uniform height to prevent the formation of opens or shorts. In the semiconductor industry, uniform solder bump height is achieved by fabricating a pillar/thick layer of Under Bump Metal (UBM) on the chip/carrier device prior to forming each solder bump. Copper, gold and nickel are among the popular materials used for UBM due to their conductivity at room temperature and their ability to provide structural support to the corresponding solder bumps. However, neither gold nor copper are superconducting metals. Non-superconducting materials such as gold and copper are undesirable in superconducting chip bonding as such materials will exhibit resistivity at cryogenic temperatures which produces heat that may hinder effective signal transmission and/or circuit performance. Furthermore, non-superconducting metals such as gold or copper can interrupt a continuous superconducting current path due to their electrical resistance.
In T. Ogashiwa et al., T. Ogashiwa et al., 1995, “Flip-Chip Bonding Using Superconducting Solder Bump,” Japanese Journal of Applied Physics, Vol. 34, 1995, pp. 4043-4046, a superconducting chip is bonded to a ceramic substrate using superconducting solder bumps. Wirings of copper lines are coated with a superconducting solder, such as an 80/20 mixture of Pb/Sn, and there are no pillars of UBM that provide structural support to the solder bumps which could result in non-uniform solder bump heights producing unintentional shorts, floating signals, and so forth.
In U.S. Pat. No. 5,440,239, a transferrable solder bump technique is introduced for assembly of semiconductor Multi Chip Module (MCM) substrates. A semiconductor die/chip employing normal metal conductors (e.g., copper, gold, etc.) is first attached to a test board using transferable solder bumps. Coupling between the solder bumps and the test board is mediated by a chrome oxide layer such that, when the chip is subsequently detached from the test board, the solder bumps transfer to the chip (i.e., separate from the chrome oxide layer) and are re-usable for future chip bonding. Such a technique may be suited well for semiconductor fabrication, but cannot be used in the superconductor industry due to some of the materials used being non-superconducting. There is also no mechanism for ensuring uniform solder bump height; thus, U.S. Pat. No. 5,440,239 does not teach superconductive electrical connections and does not teach uniform solder bump heights.
Clearly, these techniques for flip-chip bonding and interconnection and assembly of chips using transferable solder bumps are not ideal for testing and packaging a superconducting chip.